In a typical low IF transceiver, the transmitter portion is set at the same frequency as the local oscillator, which is used for both the receiver and transmitter. The receiver, however, needs to have its local oscillator offset from an incoming radio frequency (RF) signal by an amount equal to the IF frequency. This offset unfortunately prevents an RF loopback test because the transmitter is always at the same frequency as the oscillator and it is impractical to include another oscillator running at a frequency which is very close to that of the transmitter. Such an extra oscillator would require a separate phase-locked loop (PLL) and would consume a large area on a chip.
The testing of a typical low IF transceiver is currently performed using another chip to transmit to the device under test or use an expensive set of RF test equipment.
FIG. 1 is a block circuit diagram of a transmitter digital signal processor (DSP) 20 used in typical low IF transceivers. The DSP 20 includes look up table (LUT) based Gaussian-filtered Frequency Shift Keying (GFSK) modulator 22. The data 24 is input into the LUT modulator 22. The LUT 22 and a counter 26, that counts from zero up to N−1 where N is the number of samples per data bit, is used to look up the samples of the filtered data. The data 28 output from the LUT 22 represents an instantaneous frequency of a transmitted RF signal. The data 28 is fed to a latched phase accumulator 30. The output 32 from the accumulator 30 is the instantaneous phase of the RF transmit signal and is applied to a sine and cosine LUT 34, 36, which is a polar to rectangular conversion.
The outputs 38, 40 of the sine and cosine LUT 34, 36 are then converted by digital-to-analog converters (DACs) (not shown) to create In-phase and Quadrature (I and Q) signals of the transmitter, which are upconverted to the RF frequency.